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designEngineer's avatar
designEngineer
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

LVDS Serdes DPA FIFO reset recovery timing violation issue (Cyclone 10 GX)

I am trying to deserialize a 16 bit wide DDR data input running at 676 MHz using an LVDS SERDES IP and get recovery timing violations on the DPA FIFO resets. I am looking for help on fixing those in ...
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
6 years ago

Hi,

Is that possible for you to attached your design to look into it? Looking into the report, it would be hard to identify the problem. LVDS had two type, one is soft LVDS (supported in certain family device only) and hard LVDS, basically, not much constrain needed for hard LVDS.

You can refer to the email if you do not wish to published your design in public.

Thanks