LVDS Serdes DPA FIFO reset recovery timing violation issue (Cyclone 10 GX)

I understand that the timing violations can be cause by delay through the logic outside of the IP, however the recommendations state that the DPA FIFO should get a reset when the DPA locks and in order to do that I added these ports to the IP and use them outside the IP. I am trying to do this with as little delay as possible by using the DPA lock output almost directly as the DPA FIFO reset input. The signal is going only through a combinatorial inverter to get the polarity correct.

A suggestion of how else to do it that does not create timing violations would be greatly appreciated.

I am looking forward to hearing from your internal colleague who specializes in timing.

Thanks!