Forum Discussion
designEngineer
Occasional Contributor
Occasional ContributorLVDS Serdes DPA FIFO reset recovery timing violation issue (Cyclone 10 GX)
I am trying to deserialize a 16 bit wide DDR data input running at 676 MHz using an LVDS SERDES IP and get recovery timing violations on the DPA FIFO resets. I am looking for help on fixing those in ...
Rahul_S_Intel1
Frequent Contributor
Frequent ContributorHi ,
I am trying to explain the timing violation will not happen because of IP , the logic related to IP may create the timing violation , I am kindly requesting to check the logic behind the ip to resolve the timing issue .
Mean while I am not expert in timing , I will check with internal colleague who is expert in timing and will get back to you .
