Forum Discussion

Occasional Contributor

5 years ago

LVDS Serdes DPA FIFO reset recovery timing violation issue (Cyclone 10 GX)

I am trying to deserialize a 16 bit wide DDR data input running at 676 MHz using an LVDS SERDES IP and get recovery timing violations on the DPA FIFO resets. I am looking for help on fixing those in ...

violation_rpt.txt16 KB

KennyT_altera

Super Contributor

5 years ago

I manage to close the timing, the timing violation occur because your rx_dpa_locked[15:0] is connected back to your rx_fifo_reset[15:0]. This will cause recovery failure as there will be different clock transfer between the ports. I will attached back the design to you. You may check your email.

Forum Discussion

LVDS Serdes DPA FIFO reset recovery timing violation issue (Cyclone 10 GX)

Recent Discussions

F-Tile Ethernet Hard IP (100G)

Cyclone® 10 GX Avalon®-ST Interface for PCI Express example Simulation

Agilex-7 AXI MCDMA for PCIe hang

Can't generate F-Tile Ethernet Hard IP Design Example

Avalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP Soft Reset and Hard Reset