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designEngineer
Occasional Contributor
Occasional ContributorLVDS Serdes DPA FIFO reset recovery timing violation issue (Cyclone 10 GX)
I am trying to deserialize a 16 bit wide DDR data input running at 676 MHz using an LVDS SERDES IP and get recovery timing violations on the DPA FIFO resets. I am looking for help on fixing those in ...
KennyT_altera
Super Contributor
Super ContributorI manage to close the timing, the timing violation occur because your rx_dpa_locked[15:0] is connected back to your rx_fifo_reset[15:0]. This will cause recovery failure as there will be different clock transfer between the ports. I will attached back the design to you. You may check your email.
