Forum Discussion

Sameer-sahu's avatar
Sameer-sahu
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Issue with Connecting Intermediate Output to ALTDDIO_IN Input in FPGA Design

Hello everyone,

I'm currently working on an FPGA design project and have encountered a problem that I hope to get some guidance on. The issue arises when trying to connect one of our intermediate outputs directly to the least significant bit of the ALTDDIO_IN IP's input data port. Specifically, the error message I receive is as follows:

Error (15871): Input port DATAIN of DDIO_IN primitive "ddio:uut|altddio_in:ALTDDIO_IN_component|ddio_in_2of:auto_generated|ddio_ina[0]" must come from an I/O IBUF or DELAY_CHAIN primitive.

Here’s a simplified version of the relevant part of my design:

module try (input clk1,input reset,output [13:0]data_out);
reg [6:0]temp;
always @ (posedge clk1)
temp <= 7'b0000001;
ddio uut(
.aclr ( reset ),
.datain ( temp ),
.inclock ( clk1 ),
.dataout_h ( data_out[13:7] ),
.dataout_l ( data_out[6:0] )
);
endmodule
Pcie

8 Replies

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hello Sir,


    I'm Adzim, application engineer will assist you in this case.


    I require some information in the points below to debug this problem:-

    • Which Quartus version that you're using?
    • Which FPGA device that you're using?
    • Can you provide the IP name as in Platform Designer/Quartus?
    • Which compilation stage is failing?



    Regards,

    Adzim

    Regards,

    Adzim


    • Sameer-sahu's avatar
      Sameer-sahu
      Icon for Occasional Contributor rankOccasional Contributor
      2 years ago

      Hi Adzim

      Thanks for your response. Our actual production code is running on Quartous Prime 19.1 standard edition but this demo code is running on Quartous Prime 20.1 edition. In our Production device we are using cyclone V 5CEBA4U15C7 device. In our design we are using ALTDDIO_IN ip. Analysis and synthesis stage it is failing.

      Thanks & regards,

      Sameer

  • Sameer-sahu's avatar
    Sameer-sahu
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Hi Adzim,

    Thanks for your response. Our actual production code is running on Quartous Prime 19.1 standard edition but this demo code is running on Quartous Prime 20.1 edition. In our Production device we are using cyclone V 5CEBA4U15C7 device. In our design we are using ALTDDIO_IN ip. Analysis and synthesis stage it is failing.

    Thanks & regards,

    Sameer

    • FvM's avatar
      FvM
      Icon for Super Contributor rankSuper Contributor
      2 years ago

      Hi,
      I think the error message is rather clear. DDIO_IN is expecting input from IO-pin but you are connecting it to a register. If actually need DDR register function in fpga fabric, you build it from registers.

      • Sameer-sahu's avatar
        Sameer-sahu
        Icon for Occasional Contributor rankOccasional Contributor
        2 years ago

        Hi,

        But if we want to double the data rate of an intermediate value, then how to use this IP in our design. We are debugging something. So we attach some intermediate value as input to DDIO_IN. Can you please suggest, how to double the data rate of intermediate registor value.

        Thanks

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    2 years ago

    As mentioned, DDIO IP is only for DDR data on I/O pins. I think you simply want to have separate clocked processes.

    always @(posedge clk)

    dataout_h <= ...

    always @(negedge clk)

    dataout_l <= ...