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Sameer-sahu's avatar
Sameer-sahu
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Issue with Connecting Intermediate Output to ALTDDIO_IN Input in FPGA Design

Hello everyone, I'm currently working on an FPGA design project and have encountered a problem that I hope to get some guidance on. The issue arises when trying to connect one of our intermediate ou...
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Sameer-sahu's avatar
Sameer-sahu
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Hi Adzim,

Thanks for your response. Our actual production code is running on Quartous Prime 19.1 standard edition but this demo code is running on Quartous Prime 20.1 edition. In our Production device we are using cyclone V 5CEBA4U15C7 device. In our design we are using ALTDDIO_IN ip. Analysis and synthesis stage it is failing.

Thanks & regards,

Sameer

FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi,
I think the error message is rather clear. DDIO_IN is expecting input from IO-pin but you are connecting it to a register. If actually need DDR register function in fpga fabric, you build it from registers.