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Sameer-sahu's avatar
Sameer-sahu
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Issue with Connecting Intermediate Output to ALTDDIO_IN Input in FPGA Design

Hello everyone, I'm currently working on an FPGA design project and have encountered a problem that I hope to get some guidance on. The issue arises when trying to connect one of our intermediate ou...
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sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
1 year ago

As mentioned, DDIO IP is only for DDR data on I/O pins. I think you simply want to have separate clocked processes.

always @(posedge clk)

dataout_h <= ...

always @(negedge clk)

dataout_l <= ...