Occasional Contributor
Super ContributorHi,
I think the error message is rather clear. DDIO_IN is expecting input from IO-pin but you are connecting it to a register. If actually need DDR register function in fpga fabric, you build it from registers.
Occasional ContributorHi,
But if we want to double the data rate of an intermediate value, then how to use this IP in our design. We are debugging something. So we attach some intermediate value as input to DDIO_IN. Can you please suggest, how to double the data rate of intermediate registor value.
Thanks
Super ContributorOccasional ContributorHi,
I am using DDIO_IN ip to get the input data both in positive and negative edge of clock. E.g., let my input signal = 7'b0000001. Then I want this input signal will appear as output for both positive and negative clock. Then I will combine this two data and make it as a 14 bit output data.
E.g.,
wire [13:0]data_output;
reg [6:0]data_input;
DDIO_IN(
);
In this way I want to double the data rate of input 7 bit to 14 bits data. That's what I want to perform,
