Forum Discussion

Sameer-sahu's avatar
Sameer-sahu
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Issue with Connecting Intermediate Output to ALTDDIO_IN Input in FPGA Design

Hello everyone, I'm currently working on an FPGA design project and have encountered a problem that I hope to get some guidance on. The issue arises when trying to connect one of our intermediate ou...
Pcie
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hello Sir,


I'm Adzim, application engineer will assist you in this case.


I require some information in the points below to debug this problem:-

  • Which Quartus version that you're using?
  • Which FPGA device that you're using?
  • Can you provide the IP name as in Platform Designer/Quartus?
  • Which compilation stage is failing?



Regards,

Adzim

Regards,

Adzim


  • Sameer-sahu's avatar
    Sameer-sahu
    Icon for Occasional Contributor rankOccasional Contributor
    1 year ago

    Hi Adzim

    Thanks for your response. Our actual production code is running on Quartous Prime 19.1 standard edition but this demo code is running on Quartous Prime 20.1 edition. In our Production device we are using cyclone V 5CEBA4U15C7 device. In our design we are using ALTDDIO_IN ip. Analysis and synthesis stage it is failing.

    Thanks & regards,

    Sameer