Hello! I want to interpolate a 13.5 kHz sinus signal, which is generated with a NCO at a sampling rate of 54 Khz. I want a sampling of 5,4 MHz. So i tried to use a CIC-Filter with rate = 100. What I get at the output of the CIC-Filter is a 4.5 kHz sinus signal !! --> there is something wrong! What is the problem here ?? I tried different types of stages and delays, but I won't get a 13.5 sinus. please help me.. Thanks!

it could be useful a post of your schematic. How many samples has a single period of the high frequency sine signal at the output?

The samples at the output are ok. It has to be 400 samples right?? I proof that with an analog oscillator. Maybe you have a look at the image... Thanks for your help!

i think there is a problem with your CIC hardware, because input samples should be synchronized with c0 clock and output samples should be synchronized with c1 clock. Note this, for every input sample 100 samples must go out. In your hardware, an input sample (synchronized with c0) is read 100 times by a module clocked with c1. As you are using two clocks, in your CIC hardware a dual-clock FIFO for crossing clock domains must be included.

Ok. I was thinking in your way too. Because the differentiators has to be clocked with the lower sample rate and the integrators has to be clocked with the higher rate. But I thought the CIC-Filter would do this "clocking" automatically. The CIC-Filter generated by the MegaWizard has only one clock-input.....how should I solve the problem??...

so, you are driving in the wrong way the avalon-streaming signals. in_valid line must be asserted every 100 cycles of 54 MHz clock.

Interpolation with CIC Filter

15 Replies

Altera_Forum
Honored Contributor
17 years ago
it could be useful a post of your schematic.
How many samples has a single period of the high frequency sine signal at the output?
Altera_Forum
Honored Contributor
17 years ago
The samples at the output are ok. It has to be 400 samples right?? I proof that with an analog oscillator.

Maybe you have a look at the image...

Thanks for your help!
Altera_Forum
Honored Contributor
17 years ago
i think there is a problem with your CIC hardware, because input samples should be synchronized with c0 clock and output samples should be synchronized with c1 clock. Note this, for every input sample 100 samples must go out.

In your hardware, an input sample (synchronized with c0) is read 100 times by a module clocked with c1.

As you are using two clocks, in your CIC hardware a dual-clock FIFO for crossing clock domains must be included.
Altera_Forum
Honored Contributor
17 years ago
Ok. I was thinking in your way too. Because the differentiators has to be clocked with the lower sample rate and the integrators has to be clocked with the higher rate. But I thought the CIC-Filter would do this "clocking" automatically.
The CIC-Filter generated by the MegaWizard has only one clock-input.....how should I solve the problem??...
Altera_Forum
Honored Contributor
17 years ago
so, you are driving in the wrong way the avalon-streaming signals. in_valid line must be asserted every 100 cycles of 54 MHz clock.
Altera_Forum
Honored Contributor
17 years ago
parrado, while i agree with you conceptually this is not how the Altera generated test bench operates.

tobias, have you taken a look at the CIC generated test bench? also take a look at the output error signal in your project.
Altera_Forum
Honored Contributor
17 years ago
Aha!

@Parrado:
This could be the solution! I will try tomorrow in the lab.....in germany know it's 10:20 pm.

Thank You parrado! I will let you know if it works....

@thepancake:
I will have look at the generated testbench file and the error output too.
I will let you know tomorrow. Thanks..
Altera_Forum
Honored Contributor
17 years ago
Hello!

I tried to connect the "valid in" with the lower clock. When I set the rate to 5 it works fine. But with a higher rate like 10 or 100 I get a 4.5 kHz-Sinus....it's weird.
But I think it is the right way to "clock" the valid in, because in the "functional description" of the CIC-Filter you can see that the "valid in" is clocked too.
Altera_Forum
Honored Contributor
17 years ago
I am not fans of CIC IP cores but judging by your last work there is possibilty of error. You are supposed to drive the input data in once every 100 clks of output clk. By connecting slow clk to valid in you will violate that when clk is high since many fast clks will be enabled.
Altera_Forum
Honored Contributor
17 years ago
OK. So I should set "valid in" set to "VCC" ? How about "clken", "reset_n" and "out_ready" ..... they should be connected to "VCC" too ?

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Interpolation with CIC Filter

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