Forum Discussion
Altera_Forum
Honored Contributor
16 years agoi think there is a problem with your CIC hardware, because input samples should be synchronized with c0 clock and output samples should be synchronized with c1 clock. Note this, for every input sample 100 samples must go out.
In your hardware, an input sample (synchronized with c0) is read 100 times by a module clocked with c1. As you are using two clocks, in your CIC hardware a dual-clock FIFO for crossing clock domains must be included.