Forum Discussion
Honored ContributorHow to implement DE0 SDRAM as 2-port RAM
I currently use the tiny bit of memory on the FPGA for a computer vision project but it's way too limited. I have a stand-alone SDRAM controller from Altera (partially pasted below) but I need one more layer above that which implements this controller as a 2-port RAM entity. It seems like overkill to use QSYS with NiosII though, plus I'm not very familiar with it. What's resource will help me implement this controller as a 2-port RAM entity in the simplest way possible?
entity sdr_sdram is
generic(
ASIZE : integer := 23;
DSIZE : integer := 32;
ROWSIZE : integer := 12;
COLSIZE : integer := 9;
BANKSIZE : integer := 2;
ROWSTART : integer := 9;
COLSTART : integer := 0;
BANKSTART : integer := 20
);
port(
CLK : in std_logic; --System Clock
RESET_N : in std_logic; --System Reset
ADDR : in std_logic_vector(ASIZE - 1 downto 0); --Address for controller requests
CMD : in std_logic_vector(2 downto 0); --Controller command
CMDACK : out std_logic; --Controller command acknowledgement
DATAIN : in std_logic_vector(DSIZE - 1 downto 0); --Data input
DATAOUT : out std_logic_vector(DSIZE - 1 downto 0); --Data output
DM : in std_logic_vector(DSIZE / 8 - 1 downto 0); --Data mask input
SA : out std_logic_vector(11 downto 0); --SDRAM address output
BA : out std_logic_vector(1 downto 0); --SDRAM bank address
CS_N : out std_logic_vector(1 downto 0); --SDRAM Chip Selects
CKE : out std_logic; --SDRAM clock enable
RAS_N : out std_logic; --SDRAM Row address Strobe
CAS_N : out std_logic; --SDRAM Column address Strobe
WE_N : out std_logic; --SDRAM write enable
DQ : inout std_logic_vector(DSIZE - 1 downto 0); --SDRAM data bus
DQM : out std_logic_vector(DSIZE / 8 - 1 downto 0) --SDRAM data mask lines
);
end sdr_sdram;
Inst_frame_buffer : entity work.sdram_wrapper_frame_buffer PORT MAP(
rdaddress => rdaddress, -- IN std_logic_vector(18 downto 0);
rdclock => clk_vga, -- IN std_logic;
q => rddata, -- OUT std_logic_vector(11 downto 0)
wrclock => camera_pclk, -- IN std_logic;
wraddress => wraddress, -- IN std_logic_vector(18 downto 0);
data => wrdata, -- IN std_logic_vector(11 downto 0);
wren => wren -- IN std_logic;
);48 Replies
Altera_Forum--- Quote Start --- What's resource will help me implement this controller as a 2-port RAM entity in the simplest way possible? --- Quote End --- The SDRAM interface has only one port, so you can only use it as 1-port RAM. What you are probably after is multiple-master access to the common resource. This is possible if the two devices (masters) access the SDRAM at a rate that is slower than the SDRAM interface maximum performance. Eg., two devices accessing 100MHz SDRAM at an effective data rate of say 10MHz would work fine. Multi-master arbitration of the SDRAM interface would be done automatically for you if you use Qsys. Here's an SDRAM example to get you started. http://www.alteraforum.com/forum/showthread.php?t=45927 This does not use NIOS II. It uses the JTAG interface to allow your PC to access the SDRAM. Cheers, Dave- Altera_Forum
I checked that out. I don't where to begin to modify it to be what I need it to be though. Ideally it would all be in VHDL, no JTAG, no TCL, and the SDRAM size is different for the DE0-nano vs my regular DE0 board. Can I hire someone to make a quick VHDL wrapper for the Altera SDRAM controller I have as a 1-Port RAM entity that has multiple-master access functionality? I don't mind doing it with Qsys either but I would need a tutorial that doesn't use a JTAG interface or NiosII. It seems odd that this is such a hard thing to find..
- Altera_Forum--- Quote Start --- The SDRAM size is different for the DE0-nano vs my regular DE0 board. --- Quote End --- You can start Qsys and modify the SDRAM parameters. --- Quote Start --- Can I hire someone to make a quick VHDL wrapper for the Altera SDRAM controller I have as a 1-Port RAM entity that has multiple-master access functionality? --- Quote End --- Its not the SDRAM that provides the multiple master functionality, its the fabric created by Qsys. When you connect two masters to a slave, the fabric adds arbitration logic. --- Quote Start --- I don't mind doing it with Qsys either but I would need a tutorial that doesn't use a JTAG interface or NiosII. It seems odd that this is such a hard thing to find.. --- Quote End --- A Qsys system needs at least one master (otherwise there is no point in creating the system), and the two easiest ones to demonstrate in a tutorial are NIOS II or JTAG. What are you trying to do that is not supported by existing components. Perhaps if you could explain what you are trying to do, people on the forum can suggest options for you to look into. Cheers, Dave
- Altera_Forum
Sure. For right now, as a first step, I'm just receiving video from a board camera (ov7670), storing it in a 2-port ram that is being used as a frame buffer (but is using the extremely limited FPGA memory). At the same time the VGA entity is pulling the pixel data from that frame buffer when it needs it and displaying it on a monitor. That's it. Really simple but I need to use SDRAM. I can only store a 160x120 frame with this limited FPGA memory. I don't mind going through a QSYS tutorial to build what I need but it sure seems like I don't need NiosII nor do I need JTAG...
- Altera_Forum--- Quote Start --- For right now, as a first step, I'm just receiving video from a board camera (ov7670), storing it in a 2-port ram that is being used as a frame buffer (but is using the extremely limited FPGA memory). At the same time the VGA entity is pulling the pixel data from that frame buffer when it needs it and displaying it on a monitor. That's it. Really simple but I need to use SDRAM. I can only store a 160x120 frame with this limited FPGA memory. I don't mind going through a QSYS tutorial to build what I need but it sure seems like I don't need NiosII nor do I need JTAG... --- Quote End --- Its quite possible that you don't need to use a processor, it really comes down to how much intelligence is built into your existing components. For example, how is "I'm just receiving video from a board camera" implemented? From the looks of the ov7670 data sheet, its a VGA interface. I haven't used VGA, but from the data sheet, it looks basically like a streaming data source. In Altera's world, it can probably be considered an Avalon-ST data source, or it can be manipulated to look like one. You could write that data to SDRAM via a DMA controller, or perhaps some of the Video IP blocks, I have never looked at them, but others on the list should have. Perhaps start a new topic asking how people deal with VGA data streams, and SDRAM buffering, since that is more specific to what you are really interested in. Cheers, Dave
- Altera_Forum
I guess, but the way I originally formed the question removes the need to know the details of the project. It keeps it simple. I just need to use SDRAM as if it was a simple 1-port ram. I already have the controller and the entities the controller instantiates which is written by Altera and designed for the SDRAM chip on the development boards, I just need help with the next layer which does the job of making the interface even simpler. It would just have something like clock, address, ready, write/read, and data. Do you see what I mean? It's hard to believe that using SDRAM as a simple RAM component isn't a very common thing people do regardless of the application. Is there either a QSYS tutorial just for making SDRAM into a simpler RAM component or an SDRAM controller wrapper that already exists, or that I can hire someone to write? This has got to be so easy for someone more experienced than myself..
- Altera_Forum
"simple" is relative.
If your components were re-written to use standard Avalon-MM and Avalon-ST interfaces, then you could "simply" create a Qsys system. The SDRAM controller interface is that of an Avalon-MM slave. I'm sure you can create an instance all by itself, but that would not provide the dual-ported interface you want. You could create an Avalon-MM system with the SDRAM controller and two exported Avalon-MM master interfaces, so that Qsys will create the arbitration logic, and then you can interface to the two Avalon-MM master interfaces exported to the top-level. But if you have to interface to two Avalon-MM masters at the top-level, you may as well just create Avalon-MM master components for your existing code, and drop them into a Qsys system. Basically it comes down to how much time you want to waste "fighting" the tools. Altera and Xilinx have decided to use standardized bus interfaces (Avalon-MM, Avalon-ST, AXI4, AXI4-Lite, AXI4-Stream, etc) so that they can give their end-users system building tools like Qsys. If you have custom logic, then often its easier to modify the code to make it use a standard interface. Cheers, Dave - Altera_Forum
ok. 1. Which direction should I go in, pure VHDL, or a QSYS-based system? In the really big picture I am porting over a fairly large computer vision application. This is going to get a lot bigger and more complicated than just storing a frame in ram and sending it back out again to a VGA monitor. That's nothing. Eventually motion detection will be implemented which will be followed by a lot of other layers of custom image processing logic on top of that. RAM and FLASH (or an SD CARD) will also have to be used. I also want to do the pixel comparisons in parallel of course, that being one of the main reasons for using an FPGA. 2. So knowing that, does sticking to a purely VHDL system seem totally ridiculous?
3. Will NiosII have to be involved in a project like this? If so, why? 4. I have read a little about Avalon-MM and Avalon-ST interfaces but is there a guide that you know of for modifying the code to make it use a standard interface? - Altera_Forum--- Quote Start --- ok. 1. Which direction should I go in, pure VHDL, or a QSYS-based system? --- Quote End --- It depends on how interconnected your components are, and how reuseable your code is, and how much Altera IP you plan on using. Many systems can be separated into a "Control Plane" and a "Data Plane", where the "Data Plane" are your high-speed processing blocks (the reason you chose an FPGA), and the "Control Plane" is the part where you configure the data plane, eg., program packet sizes, monitor statistics, set coefficients (stuff that changes on a slower timescale). As soon as you try and use some Altera IP, there is a pretty good chance to have to use the Avalon-ST or Avalon-MM component interface. At that point you need to decide whether to make your custom components work within the Qsys environment, or whether they'll sit "outside" a Qsys design containing all the Altera IP. The Avalon-MM/ST interfaces are described in the Avalon Interface Standard and in the Verification IP Users Guide. If you were going to target both Altera and Xilinx devices, then you should look at the ARM AMBA AXI4 standard interfaces. Cheers, Dave
- Altera_Forum
Alright. It seems like QSYS is for projects where the developer wants to use a NiosII processor or JTAG interface. I want to focus on making the wrapper for the SDRAM controller. It is likely only an hour or less of work for someone more experienced than myself. What is the next step in getting assistance in developing this wrapper?
