Honored ContributorHello,
Could you please point to how to access Hard memory controller (external DDR3) in Cyclone V from FPGA custom logic? Which is the IP core that allows to create generate IP core instance, place a symbol on the schematics and connect my logic? Is that IP free for evaluation or licensed? I am using Lite edition of Quartus.
Honored ContributorHi,
DDR3 SDRAM Controller with UniPHY is what you need. It uses Avalon MM interface for user acces. I have used it with Lite edition.Honored ContributorThank you for response. But how then I know that this DDR3 interface is not for soft memory controller generation? Do you mean that UniPHY denotes, that it is hard memory controller? Which IP is then for soft memory controller (also in case of DDR2).
Honored ContributorIn DDR3 SDRAM Controller with UniPHY IP wizard there is an option to choose which to implement hard or soft controller. I don't have any experience with DDR2 in Cyclone V family but I think there is same otpion as in DDR3.
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