Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorHard memory controller IP for Cyclone V
Hello, Could you please point to how to access Hard memory controller (external DDR3) in Cyclone V from FPGA custom logic? Which is the IP core that allows to create generate IP core instance, ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- It actually is. In case of DDR3 consider that Cyclone V doesn't support write leveling, means the memory layout must follow DDR2 signal layout rules and you can't use DDR3 memory modules (which makes limited sense anyway because the hard memory controller is limited to 32 bit data width). --- Quote End --- I was considering the following integration board https://www.opalkelly.com/products/zem5305/ . The specification tells that DDR3 is connected to Cyclone V. Are you saying that despite they write DDR3 I should use DDR2 hard memory controller?
