Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorHard memory controller IP for Cyclone V
Hello, Could you please point to how to access Hard memory controller (external DDR3) in Cyclone V from FPGA custom logic? Which is the IP core that allows to create generate IP core instance, ...
Altera_ForumHonored Contributor
Honored ContributorThank you for response. But how then I know that this DDR3 interface is not for soft memory controller generation? Do you mean that UniPHY denotes, that it is hard memory controller? Which IP is then for soft memory controller (also in case of DDR2).
