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Honored Contributor
Honored ContributorHard memory controller IP for Cyclone V
Hello, Could you please point to how to access Hard memory controller (external DDR3) in Cyclone V from FPGA custom logic? Which is the IP core that allows to create generate IP core instance, ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I don't have any experience with DDR2 in Cyclone V family but I think there is same option as in DDR3. --- Quote End --- It actually is. In case of DDR3 consider that Cyclone V doesn't support write leveling, means the memory layout must follow DDR2 signal layout rules and you can't use DDR3 memory modules (which makes limited sense anyway because the hard memory controller is limited to 32 bit data width).
