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Altera_Forum
Honored Contributor
Honored ContributorHard memory controller IP for Cyclone V
Hello, Could you please point to how to access Hard memory controller (external DDR3) in Cyclone V from FPGA custom logic? Which is the IP core that allows to create generate IP core instance, ...
Altera_ForumHonored Contributor
Honored ContributorIn DDR3 SDRAM Controller with UniPHY IP wizard there is an option to choose which to implement hard or soft controller. I don't have any experience with DDR2 in Cyclone V family but I think there is same otpion as in DDR3.
