Honored ContributorHi!
I want to write into alter FIFO from state machine. I have registered data and wrreq signals. Now i am wondering, is it unsafe to set them both on the same clock cycle? Or should i set data first and then wrreq on next cycle? I am thinking that if i write them at same clock, some race conditon could happen, because this is the same cycle FIFO is sampling them. FPGA hurts my brain :/ Thanks!
Honored ContributorIf I understood the question correctly then you *do* want the FIFO input data and wrreq signals to arrive at the same time. That's actually what the FIFO cores in Quartus/Qsys expect in terms of timing but there might be options to have them staggered but lining up the data and write signals is the typical usage and default mode of operation.
For the data that comes out of the FIFO it depends on whether you have lookahead mode turned on. I use lookahead mode so that valid data is immediately available and I pop the FIFO with the rdreq signal. So normally the signal driving rdreq is also what I use as my clock enable on the capture register hooked up to the output port of the FIFO. I would have a look at the user guide, it has timing diagrams to show you how to time the inputs and how the outputs from the FIFO are timed depending on the parameters you pick: http://www.altera.com/literature/ug/ug_fifo.pdfHonored ContributorThank you for response BadOmen.
I did read user guide before posting and that actually made me question myself even more. From user guide: http://s27.postimg.org/5lvodaj43/timing.jpg As you can see signals change on falling edge. I would like to set them both on rising edge(because they are registered) but that is also when FIFO samples them. That is why i am confused. Thank you!Honored ContributorI think the confusion is the result of timing diagrams being functional so you are not seeing typical register switching wire/logic delays. I have attached a timing diagram that shows what the typical timing is (minus the full and empty signals). So the value 0 is written in just before the 2nd red line. Two cycles after the first write the data should be available at the output and the empty signal de-asserts which is when it's safe to start reading from the FIFO. When rdreq is asserted the FIFO is popped, and the next data becomes available.
Honored ContributorHonored ContributorI am facing a problem in a SCFIFO, I have progressed as per the functional diagram provided in the http://www.altera.com/literature/ug/ug_fifo.pdf. But still I am facing a problem while reading the first word.
My design works in following way, Initially, I am writing around 16 words at negedge of clock (which gets sampled at posedge of clock), wrreq signal also asserted at negedge of clock. After writing these 16 words, I have to start reading and also writing parallely. When I start reading, the first word I read is corrupted, rest of the words are getting correctly read. This is happening at the assertion of every read cycle. Please guide and help me. Regards, NavalHonored ContributorThat sounds like you don't have the FIFO instantiated in "show ahead" mode. Look ahead mode means as soon as the empty signal is low there is valid data at the output. If you don't use that mode I think it's called "legacy" mode which means there is a latency between when the FIFO is popped to when the valid data comes out.
On page 8 of that document you linked to you'll see the parameter I'm referring too called "lpm_showahead". I almost always use show ahead mode because it simplifies the design typically.Honored Contributor
