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Honored Contributor
Honored ContributorFIFO write, data and wreq
Hi! I want to write into alter FIFO from state machine. I have registered data and wrreq signals. Now i am wondering, is it unsafe to set them both on the same clock cycle? Or should i set da...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Initially, I am writing around 16 words at negedge of clock (which gets sampled at posedge of clock) --- Quote End --- This doesnt make much sense to me? are you doing this in the real design, or just a testbench? you should be consistant with which clock edge you use throughout the design. Can you post example code to show what you're doing?
