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Altera_Forum
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11 years ago

FIFO write, data and wreq

Hi! I want to write into alter FIFO from state machine. I have registered data and wrreq signals. Now i am wondering, is it unsafe to set them both on the same clock cycle? Or should i set da...
Altera_Forum's avatar
Altera_Forum
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8 years ago

I am facing a problem in a SCFIFO, I have progressed as per the functional diagram provided in the http://www.altera.com/literature/ug/ug_fifo.pdf. But still I am facing a problem while reading the first word.

My design works in following way,

Initially, I am writing around 16 words at negedge of clock (which gets sampled at posedge of clock), wrreq signal also asserted at negedge of clock. After writing these 16 words, I have to start reading and also writing parallely. When I start reading, the first word I read is corrupted, rest of the words are getting correctly read. This is happening at the assertion of every read cycle. Please guide and help me.

Regards,

Naval