FIFO write, data and wreq

If I understood the question correctly then you *do* want the FIFO input data and wrreq signals to arrive at the same time. That's actually what the FIFO cores in Quartus/Qsys expect in terms of timing but there might be options to have them staggered but lining up the data and write signals is the typical usage and default mode of operation.

For the data that comes out of the FIFO it depends on whether you have lookahead mode turned on. I use lookahead mode so that valid data is immediately available and I pop the FIFO with the rdreq signal. So normally the signal driving rdreq is also what I use as my clock enable on the capture register hooked up to the output port of the FIFO.

I would have a look at the user guide, it has timing diagrams to show you how to time the inputs and how the outputs from the FIFO are timed depending on the parameters you pick: http://www.altera.com/literature/ug/ug_fifo.pdf