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I think the confusion is the result of timing diagrams being functional so you are not seeing typical register switching wire/logic delays. I have attached a timing diagram that shows what the typical timing is (minus the full and empty signals). So the value 0 is written in just before the 2nd red line. Two cycles after the first write the data should be available at the output and the empty signal de-asserts which is when it's safe to start reading from the FIFO. When rdreq is asserted the FIFO is popped, and the next data becomes available.
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Thank you,this helped me understand :)
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