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Altera_Forum
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11 years ago

FIFO write, data and wreq

Hi! I want to write into alter FIFO from state machine. I have registered data and wrreq signals. Now i am wondering, is it unsafe to set them both on the same clock cycle? Or should i set da...
Altera_Forum's avatar
Altera_Forum
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8 years ago

That sounds like you don't have the FIFO instantiated in "show ahead" mode. Look ahead mode means as soon as the empty signal is low there is valid data at the output. If you don't use that mode I think it's called "legacy" mode which means there is a latency between when the FIFO is popped to when the valid data comes out.

On page 8 of that document you linked to you'll see the parameter I'm referring too called "lpm_showahead". I almost always use show ahead mode because it simplifies the design typically.