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Altera_Forum's avatar
Altera_Forum
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11 years ago

FIFO write, data and wreq

Hi! I want to write into alter FIFO from state machine. I have registered data and wrreq signals. Now i am wondering, is it unsafe to set them both on the same clock cycle? Or should i set da...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Thank you for response BadOmen.

I did read user guide before posting and that actually made me question myself even more.

From user guide:

http://s27.postimg.org/5lvodaj43/timing.jpg

As you can see signals change on falling edge.

I would like to set them both on rising edge(because they are registered) but that is also when FIFO samples them. That is why i am confused.

Thank you!