Errors when using the "MAX 10 Single-Port Triple Speed Ethernet and On- Board PHY Chip Design Example User Guide"

Hi Mansur,

Looks like you are running test using your own TSE design instead of the "MAX10_TSE_On-board_PHY_Design_Example" (max10tse_q_16_0_project) as example design TSE is connected to on board Marvell 88E1111 PHY chip, and not to HSMC connector.

For question on supported IO standard on HSMC connector

• If you refer to Max 10 dev kit user guide doc page 52 below, either 2.5V IO standard or LVDS IO standard is recommended for usage
• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-max10m50-fpga-dev-kit.pdf

For question on supported IO standard on Avalon-ST signal

• Avalon-ST is just internal signal inside FPGA. If you had plan to pull it out and connect to external FPGA ball pin then it's really up to user on how you want to use it.
• For instance, if you plan to connect it to HSMC connector then you can refer to recommended IO standard usage for HSMC in user guide doc. Avalon ST is not differential signal grouping so you should be using single ended IO standard like 2.5V instead of LVDS

Thanks.

Regards,

Deshi

HI Mansur,

I am not sure which doc that you are referring to but in attached Max10 dev kit user guide doc (page 18, table 4-18 HSMC schematic signals), I can definitely see more than 18 data bus pins on HSMC that can be used for 2.5V IO standard.

Can you double check again ?

Thanks.

Regards,

dlim

Hi Mansur,

Pls see my reply below.

1. Regarding bad signal quality on 125MHz clock

• This is purely signal integrity debug. It depends on how clean is the on board clock signal routing from FPGA output pin to on board Ethernet PHY chip.
  • You may want to check with your board designer team for debug

1. Regarding TSE IP speed change from 1000M to 100M

• If you are using the TSE reference design, then no RTL design changes is required at top level design as you can see from attached pic showing reference design is using FPGA internal PLL to switch between different clock frequency
  • to perform the TSE speed change, yes. Follow the instruction as shown in attached screenshot from Max10 TSE user guide doc to execute the correct TCL command

Thanks.

Regards,

dlim

Hi Mansur,

I believed you are referring to TSE reference design in below link.

https://fpgacloud.intel.com/devstore/platform/16.0.0/Standard/max-10-single-port-triple-speed-ethernet-and-on-board-phy-chip-design-example/

As you can see, the reference design is developed and validated in Quartus v16.0. My recommendation is to try to bring up the board and test everything in v16.0 first as v18.0 is not validated. We don't support reference design migration

1. For the v18.0 QSYS design component could not be found issue

• I take a look and found out the QSYS IP design hw.tcl files are missing. It's was available in original v16.0 reference design.
  • Attached is the design hw.tcl zip file. You can unzip and places these tcl files in "max10tse_q_18_0_std_project\platform"
  • In Platform Designer, goto tools -> Options, add in "max10tse_q_18_0_std_project\platform" in IP Serach Path. QSYS design should be refresh and you should see the design component not found issue go away

1. For the no receiving data failure debug

• Again, my recommendation is to get the reference design working first
  • Then you can slowly modify the reference design per your design requirement. If it fail, then it's easy to isolate where is the issue with the new modified design as well.

Thanks.

Regards,

dlim

Hi dlim,

Thanks for your quick reply.

Now the statistic counters in the System Console give the right amount of received and transmitted Ethernet packets.

But the packets dont show up on the receiving Ethernet port in Wireshark. Do you know why and how I could receive them there?

I configure Both FPGA's with the same tcl script.

Kind regards,

Mansur

Hi Deshi,

When using the single ended IO standard there is only a mapping of the first 16 data pin pairs of the HSMC connector of the MAX 10 Development kit and the HSMC card.

And additionally 2 extra data pin pairs D0, D1, D2 and D3.

Now I'm missing 6 data pin pairs for the Avalon-ST.

But I can't find the pin Mapping for the other data pins described in the HSMC Specification. For example D8 (pin 53) or D10 pin 55.

Is there an additional Pin mapping of the MAX 10 HSMC pins available or are these data pins limited by the 18 data pin pairs that I am using now?

Kind regards,

Mansur

Hi dlim,

I have another issue with my design. Now I am able to see the Avalon-ST signals which I mapped to the top level file top.v on my scope. But these signals do not appear as I expected (square waves) but more like sine waves.

I think that the risetime of the clock signal is not met which causes a sine wave instead of a square wave.

So I tried to test the Reference design in 100Mbit mode instead of 1000Mbit mode. But I can't seem to get the design in 100Mbit mode.

My question is: do I need to change the clock speed in the top.v file, by replacing enet_tx_125 with enet_tx_25 as clock parameter for the TSE MAC

Or can I change the clock speed through the System Console with the tcl script?

in the attachment you can see in orange the clock (enet_tx_125) which is way smaller than I expected. The green line is rx_dval, yellow line is rx_data[0] and purple is rx_data[7].

As you can see the data is not a squarewave as in my simulation.

Kind regards,

Mansur