Errors when using the "MAX 10 Single-Port Triple Speed Ethernet and On- Board PHY Chip Design Example User Guide"

Hi dlim,

I have another issue with my design. Now I am able to see the Avalon-ST signals which I mapped to the top level file top.v on my scope. But these signals do not appear as I expected (square waves) but more like sine waves.

I think that the risetime of the clock signal is not met which causes a sine wave instead of a square wave.

So I tried to test the Reference design in 100Mbit mode instead of 1000Mbit mode. But I can't seem to get the design in 100Mbit mode.

My question is: do I need to change the clock speed in the top.v file, by replacing enet_tx_125 with enet_tx_25 as clock parameter for the TSE MAC

Or can I change the clock speed through the System Console with the tcl script?

in the attachment you can see in orange the clock (enet_tx_125) which is way smaller than I expected. The green line is rx_dval, yellow line is rx_data[0] and purple is rx_data[7].

As you can see the data is not a squarewave as in my simulation.

Kind regards,

Mansur