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MDehp's avatar
MDehp
Icon for New Contributor rankNew Contributor
7 years ago

Errors when using the "MAX 10 Single-Port Triple Speed Ethernet and On- Board PHY Chip Design Example User Guide"

Hi all, When I use the MAX 10 Single-Port TSE reference design. I encounter some problems. I use version 18.0 of the reference design in Quartus 18.0. First of all when I open the design in platform...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi Mansur,

I believed you are referring to TSE reference design in below link.

https://fpgacloud.intel.com/devstore/platform/16.0.0/Standard/max-10-single-port-triple-speed-ethernet-and-on-board-phy-chip-design-example/

As you can see, the reference design is developed and validated in Quartus v16.0. My recommendation is to try to bring up the board and test everything in v16.0 first as v18.0 is not validated. We don't support reference design migration

  1. For the v18.0 QSYS design component could not be found issue
  • I take a look and found out the QSYS IP design hw.tcl files are missing. It's was available in original v16.0 reference design.
    • Attached is the design hw.tcl zip file. You can unzip and places these tcl files in "max10tse_q_18_0_std_project\platform"
    • In Platform Designer, goto tools -> Options, add in "max10tse_q_18_0_std_project\platform" in IP Serach Path. QSYS design should be refresh and you should see the design component not found issue go away
  1. For the no receiving data failure debug
  • Again, my recommendation is to get the reference design working first
    • Then you can slowly modify the reference design per your design requirement. If it fail, then it's easy to isolate where is the issue with the new modified design as well.

Thanks.

Regards,

dlim