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MDehp's avatar
MDehp
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6 years ago

Errors when using the "MAX 10 Single-Port Triple Speed Ethernet and On- Board PHY Chip Design Example User Guide"

Hi all, When I use the MAX 10 Single-Port TSE reference design. I encounter some problems. I use version 18.0 of the reference design in Quartus 18.0. First of all when I open the design in platform...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago
HI Mansur, I presume you are still testing "Avalon-ST reverse Loopback Test" TEST_ST_LB 1000M ? You may want to probe on board FPGA Ethernet TX channel to see is any data traffic coming out from FPGA TX ch to wire shark RX ch or not If data traffic is running on board then maybe could be some setting issue with wire shark Thanks. Regards, dlim
MDehp's avatar
MDehp
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6 years ago

Hi Dlim,

Yes it's still about the "Avalon-ST reverse Loopback Test" TEST_ST_LB 1000M.

I already tried to view the TX channel and RX channel signals on a scope, by measuring on the HSMC pins of the MAX 10 Development kit.

But I couldn't see any of the signals except for the FIFO RX and TX clocks. On the other pins I only detected noise.

This was the case when I used the "Standard Differential Host Pinout" of the HSMC Specification. But I geuss only the "Standard Single-Ended Host Pinout" is supported by the MAX 10 Development kit.

But now that I am trying to map the Avalon-ST signals of the TSE MAC according the Single-Ended Host Pinout I discovered that not all pin mapping is documented in the MAX 10 User Guide.

Could you confirm which Pinout I should use for the MAX 10 Development kit?

Kind regard,

Mansur