Errors when using the "MAX 10 Single-Port Triple Speed Ethernet and On- Board PHY Chip Design Example User Guide"

Hi Mansur,

Looks like you are running test using your own TSE design instead of the "MAX10_TSE_On-board_PHY_Design_Example" (max10tse_q_16_0_project) as example design TSE is connected to on board Marvell 88E1111 PHY chip, and not to HSMC connector.

For question on supported IO standard on HSMC connector

• If you refer to Max 10 dev kit user guide doc page 52 below, either 2.5V IO standard or LVDS IO standard is recommended for usage
• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-max10m50-fpga-dev-kit.pdf

For question on supported IO standard on Avalon-ST signal

• Avalon-ST is just internal signal inside FPGA. If you had plan to pull it out and connect to external FPGA ball pin then it's really up to user on how you want to use it.
• For instance, if you plan to connect it to HSMC connector then you can refer to recommended IO standard usage for HSMC in user guide doc. Avalon ST is not differential signal grouping so you should be using single ended IO standard like 2.5V instead of LVDS

Thanks.

Regards,

Deshi