Errors when using the "MAX 10 Single-Port Triple Speed Ethernet and On- Board PHY Chip Design Example User Guide"

Hi Mansur,

Pls see my reply below.

1. Regarding bad signal quality on 125MHz clock

• This is purely signal integrity debug. It depends on how clean is the on board clock signal routing from FPGA output pin to on board Ethernet PHY chip.
  • You may want to check with your board designer team for debug

1. Regarding TSE IP speed change from 1000M to 100M

• If you are using the TSE reference design, then no RTL design changes is required at top level design as you can see from attached pic showing reference design is using FPGA internal PLL to switch between different clock frequency
  • to perform the TSE speed change, yes. Follow the instruction as shown in attached screenshot from Max10 TSE user guide doc to execute the correct TCL command

Thanks.

Regards,

dlim