Cyclone 10 GX DisplayPort Rx

Hello dlim,

I attached two picture, it is for previous mail.

I captured all reconfiguration interface address and data. It looks correct.

The read and write operation repeated each channel but I captured only one channel.

I think the CDR pll doesn't lock. I checked 135MHZ clock. it is ok

Thanks

Michael

RREF pin should be 2K Resistor.

You mean the VREFB (Input reference voltage) need to connect GND because I didn't use DDR3 and I use LVDS TX only (No need VREF voltage).

Can you explain more information for very dangerous issue ?

Does it mean the chip goes to HOT ?

(FPGA consumed total current is Max less 300mA, I think it is not much but I added the heatsink).

Thank you

Michael

Hi

Thank you for recommending

I didn't use any voltage reference differcial IO. only 1.8V, 3.0V LVMOS and LVDS. So I will tie all VREF to GND. I didn't tie it to GND all other design I did before.

Thank you

Michael

Hi Michael,

Thanks for the update on VREF pins connection but anyway this is slightly off topic and VREF shouldn't impact DsiplayPort design.

Why not you focus back to debug on the transceiver refclk pin that's likely causing Rx CDR to loose lock issue ?

• Sorry but it's still not clear to me whether RREF pins is connected to 2k resistor on your board or not ?
• If NO then you need to fix it else if yes then you can try probe on transceiver refclk pin to check on the signal quality and also follow the C10 GX CDR debug guideline that I shared with you earlier

Thanks.

Regards,

dlim

Hello dlim,

I attached two picture and rx_analogreset, rx_digitalreset and rx_is_lockedtodata signal look good.

But still PC generate link failure (attached pic).

I think the failure is in DisplayPort link training sequence. I looked rx_reconfig read/write signal group and rx_link_rate_8bit appeared "14h, 0Ah, 06h. so PHY reconfiguration looks good.

Can you provide more information of DisplayPort link training sequence and aux channel access command to analyze problem ?

Any other check point do I need ?

Thanks

Michael

Hello

I have one more question about rx_analog_mappings module.

There are some output to control analog circuit ( out_dc, out_ac, out_vga) but it doesn't have analog circuit.

Thanks

Michael

Hi,

out_dc, out_ac, out_vga is referring to transceiver Rx channel PMA parameter.

• For now you can just stick with default setting as set in DP example design

I looked at your screenshot, the transceiver behaviour is still not correct.

• Both rx_is_lockedtodata and rx_digital_reset keeps on toggling high and low instead of stay stable
• That means either DP link training keeps on failing and repeating causing transceiver to keeps on resetting or CDR itself keeps on loose lock and causing the transceiver to keeps on reset itself

You priority right now is to get CDR to lock stable and not toggling else if transceiver channel functionality is failing then DisplayPort won't work as well.

• Did you had a chance to use the transceiver toolkit design to perform internal loopback to check if CDR is locked ?
  • If NO LOCK then something is seriously wrong. Pls check back the C10 Gx pin connection guideline doc
  • If LOCKED then at least you know CDR is working within FPGA internal loopback
  • Next if CDR is not locked during actual DP operation then likely it's due to board design connection or bad signal integrity issue

Side note : You can use Quartus signal tap tool to monitor the transceiver signal behaviour instead of doing on board probing

Once CDR is locked then you can dump MSA log using DP example design

• We can then find out more debug info from MSA log

It looks like you are still struggling a lot with your custom board.

• Do you want to consider to purchase C10 GX dev kit board + Bitec DP daughter card to aid in your issue debug ?

Thanks.

Regards,

dlim

Thank you for recommending.

I think to purchase C10 GX dev kit board + Bitec DP daughter card, There are many function so when I load my design, Board document doesn't show how to initialize state to avoid high current in unused pin in my design but kit board connected some part. so I can't use that kit board to verify my design. I just use circuit reference only.

I understood rx_is_lockedtodata signal behaver.

Since DP signal goes to FPGA through repeater chip (SN75DP130SSRGR) , it may be necessary to configure the repeater chip. I am not sure but I think the PC configured analog value of repeater chip through DPCD. so I didn't touch repeater chip register. If you have any information to control repeater chip (SN75DP130SSRGR), give me document.

Thank you

Michael

Hi,

Yup, Intel FPGA C10 GX dev kit board comes together with schematic and board layout file which should serve as good reference for your board design.

Regarding the control of repeater chip,

• I am sorry I don't have any doc for it as it's not Intel chip
• Reg configuration of repeater chip should be via DP example design NIOS software I2C bus design, not via DPCD but it's meaningless unless you download the the repeater datasheet to understand the repeater chip reg function

Thanks.

Regards,

dlim

Hi dlim,

The Board works perfectly. !!!

I found the last problem is DisplayPort signals was connected revelry

Thank you so much for supporting board debug

Michael