Forum Discussion
Occasional ContributorCyclone 10 GX DisplayPort Rx
Occasional ContributorRREF pin should be 2K Resistor.
You mean the VREFB (Input reference voltage) need to connect GND because I didn't use DDR3 and I use LVDS TX only (No need VREF voltage).
Can you explain more information for very dangerous issue ?
Does it mean the chip goes to HOT ?
(FPGA consumed total current is Max less 300mA, I think it is not much but I added the heatsink).
Thank you
Michael
Regular ContributorHi Michael,
By dangerous I mean if your board design connection is not done correctly then it may impact your FPGA design functionality.
For instance, does your board RREF pins has 2k resistor connection or not because I see RREF pins is floating in your pdf schematic ?
For VREF pin - the recommendation from C10 pin connection guideline doc that I shared with you is
- If VREF pins are not used, connect them to either the VCCIO in the bank in which the pin resides or GND
- You let VREF pin float which is not right but I think still fine.
- More important is did you use SSTL IO standard input pins for these IO bank or not ? If yes, then pls power up VREF pins accordingly else you can choose to connect VREF to VCCIO or GND
That's why I recommend you to review the C10 pin connection guildeline doc.
If everything is done correctly on your board design connection yet your ATX PLL in toolkit design still can't lock then you need to check following
- Ensure you are supplying correct clock frequency to ATX PLL refclk pin
- Ensure you provide the correct voltage swing as per the ATX PLL IO standard
Thanks.
Regards,
dlim
