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Michael2021's avatar
Michael2021
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Cyclone 10 GX DisplayPort Rx

Hello dlim, I modified the custom Dipalyport Receiver board. The Modified point is CLKUSR pin only DisplayPort Receiver function still doesn't work. I attached two picture. Picture 1 : cy...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

ok, looks like transceiver calibration can be completed and it's not stuck in reset mode anymore

I have 2 suggestion for you. You should isolate whether the CDR loose lock issue is caused by your board issue or your Quartus design issue.

To rule out potential board issue :

  1. Perform FPGA transceiver channel internal loopback follow by external loopback on board
    • FPGA transceiver channel internal loopback must works else there is really some issue with your board or the FPGA device itself or some manufacturing soldering contact issue
    • You can perform internal loopback using transceiver toolkit. Reference design and user guide doc is available in below link
    • https://fpgacloud.intel.com/devstore/platform/17.1.1/Pro/cyclone-10-gx-xcvr-toolkit-reference-design/
    • Once you verified to get the internal loopback working, then you can move on to check with external loopback on your board. (assuming you can perform external loopback on your board)
    • If it's failing with external loopback, then you can cross check the debug suggestion in CDR debug checklist that I shared with you in previous post

To rule out potential Quartus design issue

  1. It would be best if you can just stick with using DisplayPort Rx to Tx example design to bring up the DP Rx first before you move on to make design modification on it

Thanks.

Regards,

dlim

  • Michael2021's avatar
    Michael2021
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Hi dlim,

    I installed C10GX_toolkit_demo design kit and I got same result as mine.

    I probed internal signal as below

    pll_locked : always "L" : means doesn't locked

    locked : always " L" : this signal is IOPLL lock signal for test. but the 16MHZ clock comes out

    rx_is_lockedtodata : always "L" : same result as my design

    I attached C10GX_toolkit_demo design and Board schematic (power portion)

    I think my board has a problem in PLL function and Power connection is correct or not (?)

    Can you review where is wrong connection ?

    Thank you

    Michael

    • Deshi_Intel's avatar
      Deshi_Intel
      Icon for Regular Contributor rankRegular Contributor
      5 years ago

      Hi Michael,

      I am not power expert but I do noticed 2 main concern that alert me.

      • FPGA RREF pins (Reference resistor for fPLL, IOPLL, and transceiver) is not connected to 2Kohm Resistor then to GND. Highly suspect PLL functionality failure is caused by RREF pins connection.
      • FPGA Vref power supply pins : You may need to power up Vref pins depends on input IO pins usage (depends on IO standard)

      It's very dangerous if there is still issue with your board design. I strongly recommend you to perform full board schematic review again. Below is one good reference doc that can help you on board schematic review

      Thanks.

      Regards,

      dlim