Hi Michael,
Thanks for the update on VREF pins connection but anyway this is slightly off topic and VREF shouldn't impact DsiplayPort design.
Why not you focus back to debug on the transceiver refclk pin that's likely causing Rx CDR to loose lock issue ?
- Sorry but it's still not clear to me whether RREF pins is connected to 2k resistor on your board or not ?
- If NO then you need to fix it else if yes then you can try probe on transceiver refclk pin to check on the signal quality and also follow the C10 GX CDR debug guideline that I shared with you earlier
Thanks.
Regards,
dlim