Cyclone 10 GX DisplayPort Rx

Hi,

out_dc, out_ac, out_vga is referring to transceiver Rx channel PMA parameter.

• For now you can just stick with default setting as set in DP example design

I looked at your screenshot, the transceiver behaviour is still not correct.

• Both rx_is_lockedtodata and rx_digital_reset keeps on toggling high and low instead of stay stable
• That means either DP link training keeps on failing and repeating causing transceiver to keeps on resetting or CDR itself keeps on loose lock and causing the transceiver to keeps on reset itself

You priority right now is to get CDR to lock stable and not toggling else if transceiver channel functionality is failing then DisplayPort won't work as well.

• Did you had a chance to use the transceiver toolkit design to perform internal loopback to check if CDR is locked ?
  • If NO LOCK then something is seriously wrong. Pls check back the C10 Gx pin connection guideline doc
  • If LOCKED then at least you know CDR is working within FPGA internal loopback
  • Next if CDR is not locked during actual DP operation then likely it's due to board design connection or bad signal integrity issue

Side note : You can use Quartus signal tap tool to monitor the transceiver signal behaviour instead of doing on board probing

Once CDR is locked then you can dump MSA log using DP example design

• We can then find out more debug info from MSA log

It looks like you are still struggling a lot with your custom board.

• Do you want to consider to purchase C10 GX dev kit board + Bitec DP daughter card to aid in your issue debug ?

Thanks.

Regards,

dlim