Clocked Video Output slave control not functioning

Hi,

I could configure the clocked video output IP of version 8.0 for different modes.

i left the registers for mode 1 untouched. and configured the registers for mode 2 and then set mode-1 invalid and mode-2 valid respectively.

make sure, you are following this order.

- start clock video output IP

- set mode-2 invalid

- configure register values for mode-2

-stop clocked video output ip

-set mode-1 invalid

-set mode-2 valid

-start clocked video output IP

hope this would help.

Regards,

Foram

--- Quote Start ---

I have not successfully gotten Clocked Video Output to take dynamic configuration from it's slave port. I can use the wizard to configure it, but none of the 1-14 video modes will configure.

Yes, I set them invalid before changing the settings and then make them valid. However, according to the current mode register, it stays stuck at mode 0.

--- Quote End ---

The mode register will not change until the Clocked Video Output recieves a control packet (on it's Avalon Streaming Video port) that's resolution matches the resolution in one of the configured mode banks. Have you enabled the core and driven video into it?

Also, which version of Quartus as you using? In 8.0 there is a bug in the Clocked Video Output where it selects modes incorrectly. A known example of this is if you configure it for 3 mode banks only banks 1 and 2 will be usable, bank 3 will never be selected. Upgrading to 8.1 fixes this issue.

Gareth.

Foram,

This sequence does not appear to work for me

Am I correct in assuming set functions start with 0? (i.e. 0 is mode 1?)

I defensively coded aiming for mode "2", just in case, so I won't care if it's the 2nd or 3rd in the sequence.

My process...

// 3 modes chosen as available in wizard
Clocked_Video_Output cvo(CLOCKED_VIDEO_OUT_BASE);
while (cvo.get_output_fifo_usedw() == 0) { }
cvo.clear_fifo_underflow();
// long pause
cvo.start(true);         //start cvo
cvo.set_valid(2, false); //set mode 3 invalid (or is it 2?)
cvo.configure(2);        //configure register settings for this mode
cvo.stop(true);          //stop cvo
cvo.set_valid(0, false); //set lower modes invalid
cvo.set_valid(1, false); //set lower modes invalid
cvo.set_valid(2, true); //set my mode valid
cvo.start(true);         //start cvo

VidModeMatch register returns 0.

Possible problem.

The reference design shows 18 registers per mode, but the VIP User Guide shows 19 registers. I tried it both ways. (At one point it was returning a 4 but I still don't know why) My own data dump of the registers indicates to me it's probably 18. Tons of 1s, followed by some garbage values. The 1s end where 18 registers per mode would end. (18*14+4 registers)

The test pattern generator is generating a 640x480 progressive signal, and I am putting in 640x480 progressive in cvo.configure().

Gareth,

I am using Quartus 8.1.

Yes, I'm driving a signal in. I have many objects manipulating the image before it gets to me, though. I will go bypass all of that and just inject directly from a TPG.

Hrm... no, still stuck at mode 0.

Interestingly enough, the wizard errors out if you configure 14 Runtime configurable video modes. It accepts a 13 value.

This implies to me that mode 0 is the wizard defined (read: mandatory) one and is probably registers 4-21. A mandatory mode makes a lot of sense. This still doesn't explain why making it inactive doesn't force a rollover to mode 2.

--- Quote Start ---

Foram,

This sequence does not appear to work for me

Am I correct in assuming set functions start with 0? (i.e. 0 is mode 1?)

I defensively coded aiming for mode "2", just in case, so I won't care if it's the 2nd or 3rd in the sequence.

My process...

// 3 modes chosen as available in wizard
Clocked_Video_Output cvo(CLOCKED_VIDEO_OUT_BASE);
while (cvo.get_output_fifo_usedw() == 0) { }
cvo.clear_fifo_underflow();
// long pause
cvo.start(true);         //start cvo
cvo.set_valid(2, false); //set mode 3 invalid (or is it 2?)
cvo.configure(2);        //configure register settings for this mode
cvo.stop(true);          //stop cvo
cvo.set_valid(0, false); //set lower modes invalid
cvo.set_valid(1, false); //set lower modes invalid
cvo.set_valid(2, true); //set my mode valid
cvo.start(true);         //start cvo

VidModeMatch register returns 0.

Possible problem.

The reference design shows 18 registers per mode, but the VIP User Guide shows 19 registers. I tried it both ways. (At one point it was returning a 4 but I still don't know why) My own data dump of the registers indicates to me it's probably 18. Tons of 1s, followed by some garbage values. The 1s end where 18 registers per mode would end. (18*14+4 registers)

The test pattern generator is generating a 640x480 progressive signal, and I am putting in 640x480 progressive in cvo.configure().

--- Quote End ---

Hi William,

well, I am using direct address offset and IOWR functions to configure diffenrt output modes. (i am using Quartus 8.0 and VIP suit 8.0. )

I assumed the registers 4-22 are for the mode, configured in SOPC builder, as this was the only way to disable the pre-configured mode.

you mentioned in the last post, that registers 4-21 are for mode1 .. But registers 4-22 are for mode1. So may be you are by mistake using a wrong offset address for setting the mode valid invalid.

IOWR(MY_ALT_VIP_ITC_BASE, 41 , 0); // mode-2 invalid

IOWR(MY_ALT_VIP_ITC_BASE, 23 , 0); // non interlaced

IOWR(MY_ALT_VIP_ITC_BASE, 24 , 640); // width

IOWR(MY_ALT_VIP_ITC_BASE, 25 , 480); // height

IOWR(MY_ALT_VIP_ITC_BASE, 28 , 12); // Horizontal front porch

IOWR(MY_ALT_VIP_ITC_BASE, 29 , 64); // horizontal sync

IOWR(MY_ALT_VIP_ITC_BASE, 30 ,144); // HORIZONTAL BLANK

IOWR(MY_ALT_VIP_ITC_BASE, 31 , 10); // vertical front porch

IOWR(MY_ALT_VIP_ITC_BASE, 32 , 1); // vertical sync

IOWR(MY_ALT_VIP_ITC_BASE, 33 , 120); // vertical blank

IOWR(MY_ALT_VIP_ITC_BASE, 41 , 0); // mode-2 invalid

stop(MY_ALT_VIP_ITC_BASE,1);

IOWR(MY_ALT_VIP_ITC_BASE, 22 , 0); // mode-1 invalid

IOWR(MY_ALT_VIP_ITC_BASE, 41 , 1); // mode-2 valid

start(MY_ALT_VIP_ITC_BASE);

Beautiful! I got it working in two tries.

Once you confirmed the documentation was correct that there are 19 registers, and not 18, I implemented that and stuck with it.

I was setting back porch values (from the wizard) in the blanking setter functions. Oops. This was causing flicker.

Register number 3 is a hot register with only one bit active at any given time. So it was returning powers of 2 only. I now have my getter take the log_2 of the hot register value to correctly detect the currently active mode.

Yay!

I have exactly the same problem. I cannot modify any setting. The difference is that I go with PAL / interlaced 720x576. I have tried this:

IOWR(VOUT_BASE, 41 , 0); // mode-2 invalid

IOWR(VOUT_BASE, 23 , 1); // interlaced 4

IOWR(VOUT_BASE, 24 , 720); // F0 width 5

IOWR(VOUT_BASE, 25 , 288); // F0 height 6

IOWR(VOUT_BASE, 26 , 720); // F1 width 7

IOWR(VOUT_BASE, 27 , 288); // F1 height 8

IOWR(VOUT_BASE, 30 ,144); // HORIZONTAL BLANK 11

IOWR(VOUT_BASE, 33 , 2); // F1 vertical blank in lines 14

IOWR(VOUT_BASE, 36 , 24); // F0 vertical blank in lines 17 ??????

IOWR(VOUT_BASE, 37 , 23); // first active line 18

IOWR(VOUT_BASE, 38 , 311); // VBI rising edge line in F0 19 ?????

IOWR(VOUT_BASE, 39 , 313); // F1 rising edge line# 20

IOWR(VOUT_BASE, 40 , 0); // F1 falling edge line# 21

VO->stop(false);

// stop(VOUT_BASE,1);

IOWR(VOUT_BASE, 22 , 0); // mode-1 invalid

IOWR(VOUT_BASE, 41 , 1); // mode-2 valid

VO->start();

// start(VOUT_BASE);

No luck, nothing happens, the picture on the output is broken. It looks like some syncron problem I have.

When I try to ask what are the current settings, I get a lot '1':

interlaced: 1

active_picture_width: 1

active_picture_height: 1

active_picture_width_f1: 1

active_picture_height_f1: 1

horizontal_front_porch: 1

horizontal_sync: 1

horizontal_blanking: 1

vertical_front_porch: 1

vertical_sync: 1

vertical_blanking: 1

vertical_front_porch_f0: 1

veritcal_sync_f0: 1

veritcal_blanking_f0: 1

active_picture_line: 1

vertical_blank_rising_edge: 1

field_rising_edge_line: 1

valid: 1

It does not matter which mode I try to reach. Even if I dump the whole memory around that address, I get only ones. IMHO this is again some part from Altera what is not documented well at all.

Any help?

--- Quote Start ---

I have exactly the same problem. I cannot modify any setting. The difference is that I go with PAL / interlaced 720x576. I have tried this:

IOWR(VOUT_BASE, 41 , 0); // mode-2 invalid

IOWR(VOUT_BASE, 23 , 1); // interlaced 4

IOWR(VOUT_BASE, 24 , 720); // F0 width 5

IOWR(VOUT_BASE, 25 , 288); // F0 height 6

IOWR(VOUT_BASE, 26 , 720); // F1 width 7

IOWR(VOUT_BASE, 27 , 288); // F1 height 8

IOWR(VOUT_BASE, 30 ,144); // HORIZONTAL BLANK 11

IOWR(VOUT_BASE, 33 , 2); // F1 vertical blank in lines 14

IOWR(VOUT_BASE, 36 , 24); // F0 vertical blank in lines 17 ??????

IOWR(VOUT_BASE, 37 , 23); // first active line 18

IOWR(VOUT_BASE, 38 , 311); // VBI rising edge line in F0 19 ?????

IOWR(VOUT_BASE, 39 , 313); // F1 rising edge line# 20

IOWR(VOUT_BASE, 40 , 0); // F1 falling edge line# 21

VO->stop(false);

// stop(VOUT_BASE,1);

IOWR(VOUT_BASE, 22 , 0); // mode-1 invalid

IOWR(VOUT_BASE, 41 , 1); // mode-2 valid

VO->start();

// start(VOUT_BASE);

No luck, nothing happens, the picture on the output is broken. It looks like some syncron problem I have.

When I try to ask what are the current settings, I get a lot '1':

interlaced: 1

active_picture_width: 1

active_picture_height: 1

active_picture_width_f1: 1

active_picture_height_f1: 1

horizontal_front_porch: 1

horizontal_sync: 1

horizontal_blanking: 1

vertical_front_porch: 1

vertical_sync: 1

vertical_blanking: 1

vertical_front_porch_f0: 1

veritcal_sync_f0: 1

veritcal_blanking_f0: 1

active_picture_line: 1

vertical_blank_rising_edge: 1

field_rising_edge_line: 1

valid: 1

It does not matter which mode I try to reach. Even if I dump the whole memory around that address, I get only ones. IMHO this is again some part from Altera what is not documented well at all.

Any help?

--- Quote End ---

Hi,

i think, you haven't specified all the parameters.

address 28 - horizontal front porch

address 29 - horizontal sync

address 30 - horizontal blank

and for the vertical parameters, you haven't configured for register 34, 35, 36 , which are specially for interlaced video.

Also, picture is broken as in what ? do you get the video ??

is it that the start of video is not aligned with the screen ? you can adjust it in the TV encoder chip by adjusting registers for start of active video, horizontal position register, vertical position registers.

Hi,

Thank you for your answer.

... you haven't specified all the parameters.

address 28 - horizontal front porch

address 29 - horizontal sync

address 30 - horizontal blank

and for the vertical parameters, you haven't configured for register 34, 35, 36 , which are specially for interlaced video.

It is not needed to specify these parameters if I use embedded syncs. And with embedded syncs there is no chance to adjust anything at the video encoder, not to mention, that is unnecessary.

Broken means broken :-)) How can I specify.... So the picture is aligned well, but the inside part like a Picasso picture and everything is changing.

So, I still don't have diea how can I read the registers, then after this how can I set them. Any help is greatly appreciated!