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Honored ContributorAVALON-MM Master Template on DE2
I'm attempting to use the Avalon-MM Master Templates located at: (altera.com/support/examples/nios2/exm-avalon-mm.html) in order to control some external SDRAM on the Terasic DE2 Development board and have run into some trouble and was wondering if anyone who has experience using this can help.
In order to accomplish this task I created a Qsys system with an SDR SDRAM controller and the Master Template configured in read mode. Hooked up as shown in the qsys_system.jpg attachment. I then instantiated the system in a verilog file and wrote some very simple HDL to test If I could get a successful read. The HDL simply toggles the go pin on the master conduit for one clock cycle and then waits for user_data_available signal from the master template to go high. At this point it would dump the data to the LEDs on the board, toggle the read acknowledge back to the master and start over. I have it set to trigger on the overflow of a counter so there is lots of space between reads just incase. The problem I have though is I toggle the 'go' pin (I can see that control_done goes low when I look using SignalTap) and then it just sits waiting forever because the master never posts a read or asserts control_done. Does anyone have any idea what might be going wrong or how I can best trouble shoot it? I've been spending many hours goofing around in SignalTap trying to see what the heck is going wrong. As far as I can tell the Master isn't talking to the SDRAM controller properly, the master settings are wrong, or the SDRAM controller settings are wrong. I used the same settings for the SDRAM controller as listed in the NIOS tutorial for this board, including instantiating a seperate -3ns clock to send to the SDRAM chip seperate. Below is a snippet from my Verilog HDL that shows my process (with plenty of comments). Feel free to comment on anything I may be doing wrong here too, I'm pretty new to HDL and have to teach myself.always @(posedge CLOCK_50)
begin
if (!KEY) //Only incremement when I have button held down. (Possible it started before memory initialized before?)
read_count <= read_count + 1'b1;
end
always @(posedge CLOCK_50)
begin
if (state == 3'b000) //Idle state
begin
go <= 1'b0; //DRAM controller 'go' bit inactive at idle
FIFO_read <= 1'b0; //DRAM controller FIFO read ack
LEDG <= state; //green LED state diagnostic
if (user_data_available_from_the_master_template_0) //If there is data available for some reason
state <= 3'b010; //skip ahead to state 2
else if (read_count == 100000) //When a counter gets to this number a read will begin
begin
state <= 3'b001; //Increment to next state
go <= 1'b1; //set go signal high for one clock cycle.
LEDG <= state;
end
end
else if(state == 3'b001) //First state of read process
begin
go <= 1'b0; //go bit goes low after one clock
state <= 3'b010; //increment to next state
LEDG <= state;
end
else if (state == 3'b010) //Second state of read process
begin
if (user_data_available_from_the_master_template_0) //Stay in this state till there is some data to read
begin
state <= 3'b011; //Increment state after data is found
LEDR <= user_buffer_output_data_from_the_master_template_0; //Output the data to LEDs
FIFO_read <= 1'b1; //Send signal that acknowledges I read the FIFO
end
LEDG <= state;
end
else if (state == 3'b011) //Third state of read process
begin
state <= 3'b100; //Increment state
FIFO_read <= 1'b0; //set the ack signal low
LEDG <= state;
end
else if (state == 3'b100) //Fourth state of read process
begin
if (user_data_available_from_the_master_template_0) //If there is more data for some reason
state <= 3'b010; //Go back to state 2
else
state <= 3'b000; //Otherwise move back to idle state
LEDG <= state;
end
else // Catch all states not defined
begin
state <= 3'b000; //Send to idle state
go <= 1'b0; //Set signals to low
FIFO_read <= 1'b0;
LEDG <= state;
end
end
