AVALON-MM Master Template on DE2

Good catch, 4 used to be a valid FIFO depth but the amount of pipelining was increased and the .tcl file wasn't adjusted accordingly (oops....). For SDRAM I recommend a FIFO depth of at least 16 when you move on to doing buffer data movements. I typically choose FIFO depths based on the on-chip memory block size of the FPGA I'm using. For example on a Cyclone II (m4k memory blocks) for 16 bit wide data you could choose a FIFO depth of 512 and still use the same amount of memory as a more shallow FIFO.