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Hi,
I've run into the same (similar) problem with trying to use QDRII SRAM interface (AValon-enabled) in Qsys with Aletra's MM master read/write templates. The sims run correctly, but when I go to hadware, write transactions complte OK, but reads never return (control_done signal goes low upon asserting 'go' and never goes high again). I take it that the waitrequest from the fabric is staying high. Any clues?
The fifos are defined size 32 (someone had an issue with size '4'). In the sims the interface takes a while to complete calibration. Is it possible the same happens in real life, i.e. calibration never succeeds?
I'm using straix iv 100g dev board.
Thanks
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Did you already solve the problem or find a workaround? If not this may help you.
I recently also had problem when using the Latency-Aware-Read-Master template (LARM). I used it in a multi-master system in qsys, so arbitration has to be done.
The symptom was, that some read requests completed correctly, but at one point the system got stuck. I thought I produced a deadlock but did not find anything in my code. So i went on to debug into the QSYS fabric. It seams that the read signal is asserted one cycle to long when the LARM stops requesting data due to a full internal fifo. Normally this is not a problem because the FIFO never gets full (due to the -4 mentioned in the thread). However with arbitration, this read can causes bus grant. which is only removed when read is asserted in conjunction with a deasserted waitrequest.
In my system the nios cpu emtying the fifo, had an instruction cache miss thus also requesting bus access and becoming stalled and stopping consuming the user fifo -> deadlock, because the read signal will never be asserted any more.
the long story short - the solution:
* in the LARM ther is a signal and a register too_many_pending_reads and too_many_pending_reads_d1.
* the register is causing the extra read.
* remove the register and update all references to it by using the signal instead.
i am not sure if this is the correct solution - (i am not an avalon expert) - but for me it seems to work and i think it is plausible.
kr
Honored Contributor
