Honored Contributor
Honored ContributorI'm looking at the RTL and this is the behavior you should be seeing:
Cycle 0 --> You assert 'go' for one clock cycle and send in all the control signals Cycle 1-x --> Control_done should be low, 'x' is the number of cycles before read data returns to the read master Cycle x+1 --> Control_done should be high Cycle x + 2 --> Data should be available in the read master FIFO The reason why control_done asserts first is because it's based on all the reads being issued and read data returned. There is a little bit of latency in the FIFO which causes control_done to potentially assert before data is available. Even if data is not available it is safe to send in another read command. Have you checked the read master to see if the read signal is asserted? It could be the read master is trying to read but the SDRAM is asserting waitrequest for a long time. I also see a typo on line 179 of the "latency_aware_read_master.v" file, the sensitivity list should be "posedge clk or posedge reset" (I highly doubt this is the culprit though).
