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You should be using the "control_done" signal to determine when it's safe to send a new command and not the "user_data_available" signal. User_data_available is just a signal that tells you that at least one word of data is buffered in the internal FIFO. Control_done tells you when all the reads have completed.
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I am checking the "user_data_available" signal only to see if there is anything in the FIFO and if so, skipping to the state where I read whatever is in there by toggling the user_read_buffer signal (FIFO_read in my case). It is probably a good idea to check that control_done is asserted before issuing a read command by toggling the "go" signal though so I've changed one line to -> " else if (read_count == 100000 & control_done_from_the_master_template_0) "
I've also tried just removing the counter thing and having it as " else if (control_done_from_the_master_template_0) " but that doesn't seem to change anything.
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In your 000 state you have multiple drivers of the 'go' register. I'm kinda surprised that compiled to be honest. If 'read_count' was coded in such a way that it would never hit the value of 100000 then I can see why it was allowed to compile since the 'go' assertion would get optimized away.
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Thanks for pointing this out. I've removed the " go <=1'b0 " and just left the one that sets it in the if else. No change to the observed results.
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Are you reading multiple words of data from memory or just one at a time? If it is just one then I recommend building an Avalon read master instead since the master template is meant for reading buffers from memory.
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Forgot to mention what the configuration signals were set to. I am using the following:
wire control_fixed_location_to_the_master_template_0 = 1'b1;
wire [22:0] control_read_length_to_the_master_template_0 = 2;
wire [22:0] control_read_base_to_the_master_template_0 = 0;
At the moment I am just trying to read one 16bit word but in the future I plan to use it more thoroughly so that is why I am trying to use this instead of writing my own master.
For all that I know, the master template could be working as intended but the slave is not communicating with the SDRAM module for some reason... Just not really sure how to troubleshoot that case.
What I do know is control_done is high, I assert the go signal for one clock cycle, then I am stuck waiting for eternity in state 010 checking to see if user_data_available ever goes high.
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