Avalon MM Interface

is the additional hardware your own ip ?

The additional hardware is my own IP (not realised yet).

I edited a new component with a Avalon MM Master interface (adress[31..0],waitrequest, data[31..0], read_from_bus, arbiterlock, byteenable signals).

 
-- CorrDataReader.vhd
-- This file was auto-generated as a prototype implementation of a module
-- created in component editor.  It ties off all outputs to ground and
-- ignores all inputs.  It needs to be edited to make it do something
-- useful.
-- 
-- This file will not be automatically regenerated.  You should check it in
-- to your version control system if you want to keep it.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity CorrDataReader is
 port (
  address         : out std_logic_vector(31 downto 0);                    -- avalon_master.address
  waitrequest     : in  std_logic                     := '0';             --              .waitrequest
  data_mm         : in  std_logic_vector(31 downto 0) := (others => '0'); --              .readdata
  read_from_bus   : out std_logic;                                        --              .read
  byteenable      : out std_logic_vector(3 downto 0);                     --              .byteenable
  arbiterlock     : out std_logic;                                        --              .arbiterlock
  clk             : in  std_logic                     := '0';             --         clock.clk
  data_out        : out std_logic_vector(31 downto 0);                    --   conduit_end.export
  datavalid       : out std_logic;                                        --              .export
  onlyglass_clock : in  std_logic                     := '0';             --              .export
  onlyglass_vsync : in  std_logic                     := '0';       --              .export
  arbiterlock_in : in  std_logic                      := '0'              --              .export
 
 );
end entity CorrDataReader;
architecture rtl of CorrDataReader is
 
 
 type State_t is (READMEM, IDLE);
  signal state : State_t := IDLE;
begin
  byteenable <= "1111";
  datavalid <= '0';
 arbiterlock <= arbiterlock_in;
  process(clk, onlyglass_vsync)
  begin
    if onlyglass_vsync = '1' then
      state <= IDLE;
      read_from_bus <= '0';
    elsif rising_edge(clk) then
      
      if onlyglass_clock = '1' then   -- triggers read
      
          address <= x"0c000000"; -- sram adress
          read_from_bus <= '1';
          state <= READMEM;
       
      end if;
      if state = READMEM and waitrequest = '0' then
        --data available on readdata_in
        data_out<=data_mm;
        read_from_bus <= '0';
        state <= IDLE;
      end if;
    end if;
  end process;
 
 
  -- TODO: Auto-generated HDL template
 
 -- ADDRESSUPDATE: PROCESS(onlyglass_clock)  
 
  ---BEGIN
  --IF onlyglass_vsync = '1' THEN        -- RESET: signale initialisieren
 
    --nextaddress <= x"0c000000"; -- Startadresse SRAM
  -- ELSIF onlyglass_clock'event AND onlyglass_clock='0' THEN
  --  nextaddress<=nextaddress+0; -- immer 32 Bit = 4 Byte auslesen
  -- END IF; -- j
 
 --  address <= std_logic_vector(nextaddress);  -- muss unsigned sein
 --END PROCESS; 
end architecture rtl; -- of CorrDataReader

Is your address indeed in the SRAM space? You must be careful about one thing: as you read 32-bit values, you must divide by 4 the address that you can see in SOPC builder.

That's correct.

The address that I can see in SOPC builder is 0x0c000000.

/* Fill memory with a known pattern. */
for (int offset = 0; offset < 4096; offset+=4)
{
IOWR_32DIRECT(memory_base, offset, offset+1);
}
for (int offset = 0; offset < 4096; offset+=4)
{
pattern=IORD_32DIRECT(memory_base, offset);
}

This is what I do in the vhdl-code above. Reading from 0x0c000000 (SRAM Range: 0x0c000000-0x0c7fffff = 8MB) doesn't run. The waitrequest signal stays high.

sorry i am not a VHDL guy, only verilog HDL.

I add the SRAM-controller (the slave) to signal-Tap too. Let's see, what happens. I'll report here.