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Altera_Forum
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16 years ago

Avalon MM Interface

Hi, I'm using a Nios2 processor as an avalon memory mapped master. The Nios2 is connected to a avalon mm slave, which is the controller for a sram. Now I can read and write from Nios2 to the s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

This is what I do in the vhdl-code above. Reading from 0x0c000000 (SRAM Range: 0x0c000000-0x0c7fffff = 8MB) doesn't run. The waitrequest signal stays high.