Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Avalon MM Interface

Hi, I'm using a Nios2 processor as an avalon memory mapped master. The Nios2 is connected to a avalon mm slave, which is the controller for a sram. Now I can read and write from Nios2 to the s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

--- Quote Start ---

entity CorrDataReader is

port (

address : out std_logic_vector(31 downto 0); -- avalon_master.address

--- Quote End ---

so your address is a 32 bit signal and it must be the full address 0x0c000000.

address alignment here means the next address you can access is 0x0c000004

even if your master will only access 32 bit and the two lower adr bits will always be 0.

accessing the 4 bytes within the 32 bit is und byteenable control