Worst-Case Completion Time for PLL Dynamic Phase Shift (PHASESTEP → PHASEDONE)

Hi,
Dynamic Phase Shifting paragraph in Cyclone IV device handbook explains that step timing is set by a combination of Scanclk and VCO frequency. Respectively there's no simple phase step duration specification.

In a specific implementation, we are seeing about 10 scanclk cycles required for a phase step.

Regards
Frank 

Hi Frank-san,

Thank you for your reply.

SCANCLK is set to 36 MHz or 57 MHz, and VCO is configured as follows.

Could you please tell me the maximum duration under these conditions?

Regards

YY

Hi,
I can't answer the question officially. I see in simulation, that for the given parameters (fvco = 21*inclk0, scanclk = inclk0), a phase step can be performed every 3 scanclk cycles. I'm not waiting for phasedone = 0 but setting phasestep for two scanclk cycles.

Regards
Frank

Hi,

thanks to Aqid for linking Knowledge base articles about phasedone timing. It addresses the problem why some dynamic phaseshift controllers take more time per step than probably possible, also some of my previous implementations.

If you process asynchronous phasedone in a scanclock driven state machine, you need to add synchronization logic to avoid timing violations and possible metastable states. On the other hand, according to user manual, a phase step pulse of two scanclock periods, typically starting and ending at scanclk rising edge, seems sufficient to trigger a step. I also don't see cases in real hardware where phasedone is longer than one scanclk cycle, although user manual and application notes suggest it can be the case.

PLL simulation model sends phasedone of fixed 0.5 scanclk period, possibly a simplification that can't be take as a prove of hardware behaviour. But you have always a large factor between vco and scanclk frequency, maximum 100 MHz scanclk and minimum 600 MHz vco in case of Cyclone devices. Even if you utilize lower vco frequency values apparently supported by hardware (down to about 320 MHz), phasedone seems to finish within 1 scanclk period. Thus above stated sequence of one phase step per 3 scanclk cycles should work unconditionally. If you are not completely sure, you can wait another scanclk cycle, still without reading phasedone. 

Regards
Frank  

Hi,

checked phasedone timing in real hardware with MAX10, PLL block is basically identical to Cyclone III/IV and 10.

See pulsewidth of phasedone varying with fvco/fscanclk ratio. Between 0.65*tscanclk for ratio 24 (fscanclk=50 MHz, fvco=1200 MHz) and up to 1.6*tscanclk for ratio 3 (fscanclk = 100 MHz, fvco=300 MHz). 300 MHz is beyond specification but still locking. 

Means step rate of 1/4 fscanclk can be always safely achieved. Even step rate of 1/3 fscanclk works with phasedone pulse > 1*tscanclk. Apparently the requirement to await phasedone rising edge before setting phasestep isn't strict.

Phasedone rising edge shows a certain jitter against scanclk, showing that it's actually asynchronous, timed by vco.

Regards
Frank  

Hi Frank-san,

Thanks to your help, the issue has been resolved.
Thank you for your assistance and for looking into this.

Regards
yy