Worst-Case Completion Time for PLL Dynamic Phase Shift (PHASESTEP → PHASEDONE)

Question

Hello,Please tell me the maximum time between the execution of Phasestep and the completion of Phasedone.The relevant link is below.Cyclone® IV Device Handbook - Chapter 5: Clock Networks and PLLs in Cyclone IV Devices - Figure 5–26. PLL Dynamic Phase ShiftThe reason for this is that the wait time for the phase shift to complete is required in the higher-level design.Regards

fvm · Answer

Hi,Dynamic Phase Shifting paragraph in Cyclone IV device handbook explains that step timing is set by a combination of Scanclk and VCO frequency. Respectively there's no simple phase step duration specification.In a specific implementation, we are seeing about 10 scanclk cycles required for a phase step.RegardsFrank&nbsp;

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Worst-Case Completion Time for PLL Dynamic Phase Shift (PHASESTEP → PHASEDONE)

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