New Contributor
Super ContributorHi,
thanks to Aqid for linking Knowledge base articles about phasedone timing. It addresses the problem why some dynamic phaseshift controllers take more time per step than probably possible, also some of my previous implementations.
If you process asynchronous phasedone in a scanclock driven state machine, you need to add synchronization logic to avoid timing violations and possible metastable states. On the other hand, according to user manual, a phase step pulse of two scanclock periods, typically starting and ending at scanclk rising edge, seems sufficient to trigger a step. I also don't see cases in real hardware where phasedone is longer than one scanclk cycle, although user manual and application notes suggest it can be the case.
PLL simulation model sends phasedone of fixed 0.5 scanclk period, possibly a simplification that can't be take as a prove of hardware behaviour. But you have always a large factor between vco and scanclk frequency, maximum 100 MHz scanclk and minimum 600 MHz vco in case of Cyclone devices. Even if you utilize lower vco frequency values apparently supported by hardware (down to about 320 MHz), phasedone seems to finish within 1 scanclk period. Thus above stated sequence of one phase step per 3 scanclk cycles should work unconditionally. If you are not completely sure, you can wait another scanclk cycle, still without reading phasedone.
Regards
Frank
