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YY
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1 month ago

Worst-Case Completion Time for PLL Dynamic Phase Shift (PHASESTEP → PHASEDONE)

Hello, Please tell me the maximum time between the execution of Phasestep and the completion of Phasedone. The relevant link is below. Cyclone® IV Device Handbook - Chapter 5: Clock Networks and P...
Programmable Logic Device
YY's avatar
YY
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1 month ago

Hi Frank-san,

Thank you for your reply.

SCANCLK is set to 36 MHz or 57 MHz, and VCO is configured as follows.

Could you please tell me the maximum duration under these conditions?

Regards

YY