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YY's avatar
YY
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13 hours ago

Worst-Case Completion Time for PLL Dynamic Phase Shift (PHASESTEP → PHASEDONE)

Hello, Please tell me the maximum time between the execution of Phasestep and the completion of Phasedone. The relevant link is below. Cyclone® IV Device Handbook - Chapter 5: Clock Networks and P...
Programmable Logic Device
FvM's avatar
FvM
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6 hours ago

Hi,
Dynamic Phase Shifting paragraph in Cyclone IV device handbook explains that step timing is set by a combination of Scanclk and VCO frequency. Respectively there's no simple phase step duration specification.

In a specific implementation, we are seeing about 10 scanclk cycles required for a phase step.

Regards
Frank