To build a FIFO using SRAM

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From your previous post, you said i need to design the input port for Avalon ST? I don't quite know how to start.

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The ADC has no support for back-pressure, and it has valid data on every clock, so an Avalon-ST source component is basically;

aso_data <= adc_data;

aso_valid <= '1';

If you have to use control registers to setup the ADC, then that would involve an Avalon-MM slave registers interface.

The next step is to use SOPC Builder or Qsys to create the _hw.tcl file to recognize this component as an SOPC component. Use the templates provided within that tool.

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Can i use PIO core to supply the stream or a DCFIFO(input from ADC and output to ST sink of SGDMA) ?

If i transfer from DCFIFO to SRAM, can i use memory-to-memory configuration of SGDMA?

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You cannot use the PIO component. You need your own custom Avalon-ST component as described above. You should be able to use the SGDMA controller to connect the Avalon-ST port of the ADC to the Avalon-MM interface on the SRAM.

Alternatively, you can create an Avalon-MM master for the ADC interface, and use that to write to the SRAM. But in that case, you would need to include rate-matching FIFOs. The SGDMA controller should have that already (or the fabric that gets created will have it).

Cheers,

Dave

Dave,

So, basically.. this is just to create an input port for ADC data to enter to the SGDMA core in the SOPC built block?

I kind of know what you are trying to say, after spending some time in SOPC builder.

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aso_data <= adc_data;

aso_valid <= '1';

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Why is the valid bit asserted all the time? it does not go invalid? then whats the point of having a valid bit?

Since you said the process is quite easy, do you think you can make this component in SOPC and send it to me? i really need to look at examples to learn to do it right, so many things can go wrong the first time. This is very new to me.

Thanks!

Michael

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So, basically.. this is just to create an input port for ADC data to enter to the SGDMA core in the SOPC built block?

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The block is to get the ADC into SOPC Builder as an Avalon-ST source. From there you can make a connection to an Avalon-ST sink.

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Why is the valid bit asserted all the time? it does not go invalid? then whats the point of having a valid bit?

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Avalon-ST interfaces normally have ready, valid, and data signals. Its generally just easier to include them all. Whether you implement them, depends on what you are trying to do. For a quick-and-dirty test, not implementing them is fine.

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Since you said the process is quite easy, do you think you can make this component in SOPC and send it to me? i really need to look at examples to learn to do it right, so many things can go wrong the first time. This is very new to me.

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Here's an example from the Stratix II DSP kit. I was connecting this ADC to an Avalon-ST sink that would accept data on every clock, so I did not need to implement backpressure. I was also using an SOPC clock that was the same frequency as the ADC. If your ADC is running at a different frequency, and with a different width, then you could add a dual-clock FIFO to this component, and then you would implement the ready/valid controls based on FIFO status bits.

Note: the _hw.tcl file uses a relative path to the .vhd source, since I keep the _hw.tcl files in a scripts/ folder, and the VHDL in a src/ folder for each project.

Cheers,

Dave

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I was also using an SOPC clock that was the same frequency as the ADC. If your ADC is running at a different frequency, and with a different width, then you could add a dual-clock FIFO to this component, and then you would implement the ready/valid controls based on FIFO status bits.

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First of all, thank you very much on the example file you sent me, it is very helpful.

From you post, if i use the ADC as an Avalon-ST source in SOPC builder, can i connect it to a SGDMA core directly? since SGDMA has its own FIFO? Ultimately, I want to fill ADC data to the SRAM with SGDMA as fast as possible(hopefully at ADC sampling speed).

Could the SGDMA read ADC data, store in its FIFO, and write to its connected SRAM simultaneously? i mean, is it dual clock capable?

Thanks,

Michael

IIRC, the SGDMA component is not dual clock capable.

You need to put a dual clock fifo component between the ADC and the SGDMA component.

And you need to run the SGDMA and memory controller at a higher clock frequency than your ADC.

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From you post, if i use the ADC as an Avalon-ST source in SOPC builder, can i connect it to a SGDMA core directly? since SGDMA has its own FIFO? Ultimately, I want to fill ADC data to the SRAM with SGDMA as fast as possible(hopefully at ADC sampling speed).

Could the SGDMA read ADC data, store in its FIFO, and write to its connected SRAM simultaneously? i mean, is it dual clock capable?

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If the SGDMA controller is not sufficient, then write your own component using dual-ported RAM or a dual-clock FIFO.

Before attempting to implement anything in hardware, you should simulate your design to see how well clock-domain crossing is implemented.

Cheers,

Dave