To build a FIFO using SRAM

Dave,

So, basically.. this is just to create an input port for ADC data to enter to the SGDMA core in the SOPC built block?

I kind of know what you are trying to say, after spending some time in SOPC builder.

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aso_data <= adc_data;

aso_valid <= '1';

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Why is the valid bit asserted all the time? it does not go invalid? then whats the point of having a valid bit?

Since you said the process is quite easy, do you think you can make this component in SOPC and send it to me? i really need to look at examples to learn to do it right, so many things can go wrong the first time. This is very new to me.

Thanks!

Michael